As the Semiconductor industry is entering the era that foresees the end of miniaturization of the Silicon transistor, engineers are already considering newer approaches to boost the device density, the efficiency, and the performance of the logic and memory Chips without necessitating the move to smaller transistors. Although Three-Dimensional (3D) circuits are nothing new given that Integrated-Circuits (ICs) are routinely packaged nowadays one on top another via wire-bonds or large copper pillars called Through-Silicon-Via's (TSV's) that vertically connect the ICs together, the concept has still limitations. For one thing, these 3D-Packages are interconnecting the subsystems and not their discrete components. This is consequently limiting the density of 3D interconnections and the overall Chip performance. Further, even in substituting wire-bonds with TSV's the resulting effects from RC delays and higher impedances between subsystems were reported to still impose reduced electrical performance, high parasitic power consumption, and poor heat dissipation. Among the many published literatures detailing on these effects are those by Pulkit Jath et al., “Three Dimensional Integrated Circuit Design”, Chapter 3: Thermal and power delivery Challenges in 3D ICs, pp. 33-61, Springer Science+Business Media, LLC, 2010; and Mohammad A. Ahmed et al., “Delay and power optimization with TSV-aware 3D floorplanning”, 2014 15th International Symposium on Quality Electronic Design (ISQED), pp. 189-196, Santa Clara, Calif., March 2014.
Today's cutting-edge Integrated-Circuits have only recently started allowing full monolithic vertical stacking of the active transistors on top of each other. Method to this vertical monolithic integration use exact same technique that is utilized nowadays in the standard commercial productions of the Silicon-On-insulator (SOI) wafers, that is: The Smart-Cut approach, also known as, Ion-Cut, or Layer-Transfer. It was initially described and demonstrated by M Bruel, B. et al., “Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding”, Japanese Journal of Applied Physics, 36, 1636, 1997, and was being continuously improved upon over the past 20 years. Several Patents are already filed on the manufacturing of monolithic 3D-ICs using this Smart-Cut approach, among which are the works by, Zvi Or-Bach et al., U.S. Pat. No. 9,564,432 B2, “3D Semiconductor Device and Structure”, Feb. 7, 2017, and, Zvi Or-Bach, U.S. Pat. No. 9,577,642 B2, “Method to Form a 3D Semiconductor Device”, Feb. 2, 2017. The core concept in these newly filed patents is founded on vertically stacking through Smart-Cuts thin layers of virtually defect-free Silicon; with their Inline dielectrics firmly bonded together and sandwiched between these layers. The active transistors are designed and built on these vertically stacked thin layers of silicon that are separated from each other with inline dielectrics and Metal interconnects. Vertical TSVs cut through these stacked layers of silicon and vertically wire transistors together. Early gross results from this method to monolithic 3D integration already reported on much shorter overall wires between transistors. This appears to already tackle the well-known wire-delay problems in today's commercial ICs and that are caused from no other than the inter-wirings of the transistors through multi layers of Metals and thick inline dielectrics. It was specifically reported that more than an order of magnitude improvement in the “Power×Area×Delay” figure-of-merit does result. Also reported were ˜34% consequent shorter wire-lengths, ˜26% improvement in power consumption, and more than 50% reduction of die-area. Relating findings were reported by Zhou et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density-parity-check code decoder in three-dimensional integrated circuits”, Proceedings of the 25th IEEE International Conference on Computer Design (ICCD), pp. 194-201, October 2007, and, Neela Lohith Penmetsa et al., “Low Power Monolithic 3D IC Design of Asynchronous AES Core”, Proceedings of the 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, May 2015. This same monolithic stacking of transistors also demonstrated strong potential to the continuation of Moore's law by continuously increasing the number of transistors per unit-area through this vertical expansion. Gains in device densities that are equivalent to two generations of Dennard scaling were reported by Synopsys, Proceedings of the 3D Architectures for Heterogeneous Integration and Packaging, December 2010.
Despite all the above enhancements more power-efficient high-speed eDcircuits still require more reduced RC delays and shorter interconnects. Capacitive coupling through the dielectric sidewalls between the TSVs and the silicon substrates was still reported to impose limitation on higher speed. This was described in many literatures among which is the work by, Dae Hyun Kim et al., “Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling”, IEEE Trans. Comp. Pack. Manuf. Tech., vol. 1, no. 2, February. 2011.
Additionally, the use of these large bulky TSVs to vertically connect devices together can have many related manufacturing snags. It also offers a rather limited potential to vertically monolithically integrate in high volume the components (e.g. transistors) together.
The long established approach to increasing the CPU performance prior to the 180 nm CMOS technology node was to reduce the device Gate length so to drastically boost this device performance which consequently boosted overall CPU speed (or performance). After the 90 nm node RC delays from the Backend process started to significantly dominate the CMOS speed. Reduction of the Gate lengths no longer increased device level speed but rather enabled denser device level integrations. This trend of continuously increasing the Cache memory through denser device level integrations has been continuing since generation after generation following the prediction of Moore's law and it did enable continuous faster computations. This also paved way to the monolithic multi-coring of CPUs and exploited the computational parallelisms in a single chip die. This trend of continuously multi-coring monolithically and increasing the Cache size is still the standard that is adopted today to increase computational parallelisms and boost the computing speed in today's microprocessors. Major hurdle of that approach is however that this trend cannot continue forever. It is well established today that the transistors Gate length will no longer shrink beyond the 5 nm process technology (5 nm node). This will ultimately cause the size of future microprocessor dies to start increasing drastically shall this “brute-force” trend of continuously multi-coring and increasing the Cache size continue. Aside from this foreseen limitation, the today's microprocessors have become highly energy-inefficient. This is simply because of their very high transistor-counts that are causing the off-state or leakage (standby) power in the transistors to start dominating the total consumed power. Their active power is also no longer converting efficiently to performance because of Backend delays. Smarter ways to realizing denser device level integrations and faster computations are crucially needed today.
Reduced RC delays with denser device level integrations through fully monolithic three-dimensional (ICs) can be the ultimate realizable long-term approach to this dilemma that is plaguing the semiconductor industry today. Added device level control that intelligently optimizes the power consumed in the modules of these ICs and alternates their operation between a standby mode and high performance can provide further substantial boost to both power-efficiency and highest performance.